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this document provides an overview of the mpc565/mpc566 microcontrollers, including a block diagram showing the major modular components, sections that list the major features, and differences between the mpc565/mpc566 and the mpc555. the mpc565 and mpc566 devices are members of the motorola mpc500 risc microcontroller family. the parts herein will be referred to only as mpc565 unless specific parts need to be referenced. 1 introduction the mpc565 device offers the following features: ?powerpc ? core with a floating point unit (fpu) and a burst buffer controller (bbc) unified system integration unit (usiu), a flexible memory controller, and improved interrupt controller 1 mbyte of flash memory (uc3f) ? typical endurance of 100,000 write/erase cycles @ 25oc ? typical data retention of 100 years @ 25oc 36 kbytes of static ram (two calram modules) ? 8 kbytes of normal access or overlay access (sixteen 512-byte regions) ? 4 kbytes in calram a, 4 kbytes in calram b three time processor units (tpu3) ? tpu3 a and tpu3 b are connected to dptram ab (6 kbytes) ? tpu3 c is connected to dptram c (4 kbytes) a 22-timer channel modular i/o system (mios14) ? same as mios1 plus a real-time clock sub-module (mrtcsm), 4 counter sub-modules (mcsm), and 4 pwm sub-modules (mpwmsm) three toucan modules (toucan_a, toucan_b, and toucan_c) two enhanced queued analog to digital converters (qadc64e a, qadc64e b) with analog multiplexers (amux) for 40 total analog channels. these modules are configured so each module can access all 40 of the analog inputs to the part. table 1. mpc565/mpc566 features device flash code compression mpc565 1 mbyte code compression not supported mpc566 1 mbyte code compression supported product brief mpc565pb/d rev. 3, 2/2003 mpc565/mpc566 product brief f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2 mpc565/mpc566 product brief motorola block diagram two queued serial multi-channel modules (qsmcm a, qsmcm b), each of which contains a queued serial peripheral interface (qspi) and two serial controller interfaces (sci/uart) -40 c ? 125 c ambient temperature, -40 c ? 85 c for suffix c devices, -55 c? 125 c for suffix a devices debug features: ? a j1850 (dlcmd2) communications module ? a nexus debug port (class 3) ? ieee-isto 5001-1999 ? jtag and background debug mode (bdm) packaging and electrical 1.1 block diagram figure 1 is a block diagram of the mpc565. figure 1. mpc565 block diagram e-bus powerpc core l-bus u-bus imb3 flash 512 kbytes + fp usiu flash 512 kbytes l2u i/f uimb qsmcm mios14 dptram 6 kbytes readi jtag tpu3 qadc64e qsmcm tpu3 dptram 4 kbytes tpu3 to u dlcmd2 32 kbyte calram a 4 kbyte overlay 4 kbyte calram b 4 kbyte overlay can to u can tou can w/amux qadc64e w/amux buffer burst controller 2 decram (4kbytes) 28 kbytes sram no overlay f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mpc565/mpc566 product brief 3 detailed feature list 1.2 detailed feature list the mpc565 key features are explained in the following sections. 1.2.1 high performance cpu system fully static design four major power saving modes ? on, doze, sleep, deep-sleep and power-down 1.2.2 risc mcu central processing unit (rcpu) high-performance core ? powerpc single issue integer core ? precise exception model ? floating point ? code compression (mpc566 only) ? compression reduces usage of internal or external flash memory ? compression optimized for automotive (non-cached) applications ? new compression scheme decreases code size to 40% ?50% of source 1.2.3 mpc500 system interface (usiu) mpc500 system interface (usiu, bbc, l2u) periodic interrupt timer, bus monitor, clocks, decrementer and time base clock synthesizer, power management, reset controller external bus tolerates 5-v inputs, provides 2.6-v outputs enhanced interrupt controller supports a separate interrupt vector for up to eight external and 40 internal interrupts ieee 1149.1 jtag test access port bus supports multiple master designs usiu supports dual-mapping of flash to move part of internal flash memory to external bus for development external bus, supporting non-wraparound burst for instruction fetches, with up to 8 instructions per memory cycle 1.2.4 burst buffer controller (bbc) module exception vector table relocation features allow exception table to be relocated to following locations: ? 0x0000 0000 - 0x0000 1fff (normal mpc500 exception table location) ? 0x0001 0000 - 0x0001 1fff (0 + 64 kbytes; second page of internal flash) ? second internal flash module ? internal sram ? 0x0fff_0100 (external memory space; normal mpc500 exception table location) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4 mpc565/mpc566 product brief motorola detailed feature list 1.2.5 flexible memory protection unit flexible memory protection units in bbc (impu) and l2u (dmpu) default attributes available in one global entry attribute support for speculative accesses 1.2.6 memory controller flexible chip selects via memory controller 24-bit address and 32-bit data buses 4- to 16-mbyte (data) or 4-gbyte (instruction) region size support four-beat transfer bursts, two-clock minimum bus transactions use with sram, eprom, flash and other peripherals byte selects or write enables 32-bit address decodes with bit masks four instruction regions four data regions 1.2.7 1 mbyte of cdr3 flash eeprom memory (uc3f) 1 mbyte flash ? two uc3f modules, 512 kbytes each page mode read block (64-kbyte) erasable external 4.75- to 5.25-v vpp program and erase power supply typical endurance of 100,000 write/erase cycles @ 25oc typical data retention of 100 years @ 25oc 1.2.8 36-kbyte static ram (calram) 36-kbyte static calibration ram ? composed of 4-kbyte and 32-kbyte calram modules fast access: one clock keep-alive power soft defect detection (sdd) 4 kbyte calibration (overlay) ram per module (8 kbytes total) eight 512-byte overlay regions per module (16 regions total) 1.2.9 general purpose i/o support (gpio) general-purpose i/o support address (24) and data (32) pins can be used as gpio in single-chip mode 16 gpio in mios14 many peripheral pins can be used as gpio when not used as primary functions 5-v outputs with slew rate control f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mpc565/mpc566 product brief 5 detailed feature list 1.2.10 debug features extensive system debug support on-chip watchpoints and breakpoints program flow tracking background debug mode (bdm) 1.2.10.1 nexus debug port (class 3) nexus/ieee ? isto 5001-1999 debug port (class 3) nine- or 16-pin interface 1.2.10.2 message data link controller (dlcmd2) module two pins muxed with qsmcmb pins. muxing controlled by qsmcmb pcs3 pin assignment register sae j1850 class b data communications network interface compatible and iso compatible for low-speed ( < 125 kbps) serial data communications in automotive applications 10.4 kbps variable pulse width (vpw) bit format digital noise filter, collision detection hardware cyclical redundancy check (crc) generation and checking block mode receive and transmit supported 4x receive mode supported (41.6 kbps) digital loopback mode in-frame response (ifr) types 0, 1, 2, and 3 supported dedicated register for symbol timing adjustments inter-module bus 3 (imb3) slave interface power-saving imb3 stop mode with automatic wakeup on network activity power-saving imb3 clockdis mode debug mode available through imb3 freeze signal or user controllable soft_frz bit polling and imb3 interrupt generation with vector lookup available 1.2.11 integrated i/o system true 5-v i/o 1.2.11.1 time processor units (tpu3) three time processing units (tpu3) ? 16 channels each each tpu3 is a microcoded timer subsystem one 6-kbyte and one 4-kbyte dual-port tpu ram (dptram), one (6-kbyte) shared by two tpu3 modules for tpu microcode and the 4-kbyte dedicated to the third tpu3 for microcode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
6 mpc565/mpc566 product brief motorola detailed feature list 1.2.11.2 22-channel modul ar i/o system (mios14) 22-channel mios timer (mios14) six modulus counter submodules (mcsm) ? four additional mcsm submodules compared to mios1 10 double action submodules (dasm). 12 dedicated pwm submodules (pwmsm) ? four additional pwm submodules compared to mios1 (shared with mios gpio pins) mios real-time clock submodule (mrtcsm) provides low power clock/counter ? requires external 32-khz crystal ? uses four pins: two for 32-khz crystal, two for power/ground. 1.2.12 two enhanced queued analog-to-digital converter modules (qadc64e) two enhanced queued analog to digital converters (qadc64e a, qadc64e b) with amuxes for 40 total analog channels. 10 bit a/d converter with internal sample/hold ? typical conversion time is 4 s (250-kbyte samples/sec) ? two conversion command queues of variable length automated queue modes initiated by: ? external edge trigger/level gate ? software command ? periodic/interval timer, assignable to both queue 1 and 2 64 result registers in each qadc64e module ? output data is right or left justified, signed or unsigned synchronized clock mode allows both qadc64es to see the same conversion clock. this allows the two modules to look like one large qadc with four queues. conversions alternate reference (altref) pin. this pin can be connected to a different reference voltage 1.2.13 three can 2.0b controller (toucan) modules three toucan modules (toucan_a, toucan_b, and toucan_c) 16 message buffers each, programmable i/o modes maskable interrupts programmable loopback for self-test operation independent of the transmission medium (external transceiver is assumed) open network architecture, multimaster concept high immunity to emi short latency time for high-priority messages low power sleep mode, with programmable wake up on bus activity toucan_c pins shared with mios14 gpio pins f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mpc565/mpc566 product brief 7 detailed feature list 1.2.14 queued serial multi-channel modules (qsmcm) two queued serial modules with one queued-spi and two sci each (qsmcm_a, qsmcm_b) ? qsmcm_a matches full mpc555 qsmcm functionality ? qsmcm_b has pins muxed with dlcmd2 module ? two pins are muxed with dlcmd2 (j1850) transmit and receive pins (b_pcs3_j1850_tx and b_rxd2_j1850_rx) ? qsmcm b vs j1850 mux control provided by qpapcs3 bit in qsmcm pin assignment register (pqspar) queued-spi ? provides full-duplex communication port for peripheral expansion or interprocessor communication ? up to 32 preprogrammed transfers, reducing overhead ? synchronous serial interface with baud rate of up to system clock / 4 ? four programmable peripheral-select pins support up to 16 devices ? special wrap-around mode allows continuous sampling of a serial peripheral for efficient interfacing to serial analog-to-digital (a/d) converters sci ? uart mode provides nrz format and half- or full-duplex interface ? 16 register receive buffer and 16 register transmit buffer on one sci ? advanced error detection, and optional parity generation and detection ? word length programmable as 8 or 9 bits ? separate transmitter and receiver enable bits, and double buffering of data ? wake-up functions allow the cpu to run uninterrupted until either a true idle line is detected, or a new address byte is received 1.2.15 electrical specifications and packaging 40 mhz operation (56 mhz operation is optional for the mpc566) -40 c ? 125 c ambient temperature, -40 c ? 85 c for suffix c device, -55 c? 125 c for suffix a devices 2.6 v 0.1 v external bus ? external bus is compatible with external memory devices operating from 2.5 v to 3.4 v. ? extended voltage range (2.7 ? 3.4 v) degrades data drive timing by 1.1 ns on date writes. 2.6 0.1 v internal logic 5-v i/o (5.0 0.25 v) available in package or bumped die plastic ball grid array (pbga) packaging ? 388 ball pbga ? 27 mm x 27 mm body size 1.0 mm ball pitch f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
8 mpc565/mpc566 product brief motorola mpc565 optional features 1.3 mpc565 optional features the following features of the mpc565 are optional features and may not appear in certain configurations: 56-mhz operation (40-mhz is default) mpc566 supports code compression 2 differences between the mpc565 and the mpc555 the mpc565 is an enhanced version of the mpc555. most functional features of the mpc555 are unchanged on the mpc565. table 2 shows the high level differences. table 2. differences between modules of the mpc555 and the mpc565 module mpc555 mpc565 cpu core no change bbc bbc bbc with improved code compression 1 1 available on some options. l2u no change sram 26-kbytes 36-kbyte calram with overlay features flash 448-kbyte cmf 1-mbyte uc3f (new programming, etc.) usiu usiu usiu with enhanced interrupt controller jtag no change readi none new module uimb no change qadc64 2 qadc64 (16 channels on each qadc for 32 total channels) 2 qadc64e w/amuxes ( 40 channels accessible from either qadc64e) qsmcm (1) no change (2) dlcmd2 (j1850) none 1 mios mios1 mios14: mios1 with real-time clock (mrtcsm), 4 more pwmsms and 4 more mcsms toucan (2) no change (3) tpu3 (2) no change (3) dptram (6-kbytes) no change (6-kbytes, 4-kbytes) power supplies ? 40 mhz with two power supplies: nominal 3.3-v to 5.0-v power supplies 56 mhz with two power supplies: 5.0-v i/o, 2.6-v internal logic f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mpc565/mpc566 product brief 9 additional mpc565 differences 2.1 additional mpc565 differences the following are additional differences between the mpc555 and the mpc565. spi (miso, mosi, and sck) pin drive. ? mpc565 provides 21-ns rise/fall with 200-pf load using cmos (20%/70%) levels gpio on modck1 pin outputs only 2.6 v ? modck1 pin is in keep-alive power section with no 5-v rail available ? 5.0-v compatibility modes ? input is 5-v friendly ? 2.6-v output has less slew rate control ? 2.6-v: voh = 2.3 v power supplies for external bus pins ? qvddl is quiet supply to hold non-switching outputs quiet even when noisy supply (nvddl) sags ? qvddl supplies pre-drive and other pad logic ? nvddl only supplies final pmos driver stage ? qvddl and nvddl shorted on customer board after filtering pull-up and pull-down changes during poreset and hreset ? all 2.6-v/5-v pads (external bus: address/data/control) pull down at reset ? all 5-v pads pull up at reset ? additional control granularity in the pdmcr register no pull-ups on qsmcm sci receive pads a_rxd1_qgpi1, a_rxd2_qgpi2, b_rxd1_qgpi1 pins do not have weak pull-up during reset or any other time clkout has 3 drive strength options ? better matches drive to requirements to reduce emi ? 25, 50, 100 pf instead of 45 and 90 pf change reset value of engclk to maximum divide (crystal/128) ? for a 4-mhz crystal, this is 31.25 khz ? engclk is selectable between 2.6 v and 5 v a daisy chain between uc3f modules allows either module to provide the reset configuration word (rcw) censorship operation ? a rcw bit controls whether or not the entire uc3f can be erased while censorship is violated bbc sprs (ppc regs) access in two clocks instead of one clock calram internal protection block size is 8 kbytes ? instead of 4 kbytes on mpc555 lram calram causes machine check exception instead of data storage interrupt (dsi) exception in certain cases ? for non-overlay cpu core accesses, a dsi exception is taken ? for overlay accesses and any non-core access (slave mode), a machine check exception is taken f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
10 mpc565/mpc566 product brief motorola additional mpc565 differences calram causes dsi exception only if the data relocation (dr) bit in the core machine state register, msr[dr], is set. ? l2u on mpc555 already followed this protocol, but the lram did not. now all l-bus peripherals follow this protocol. ? the msr[dr] bit is described in the reference manual for more information. four additional prds control bits were added to the usiu to allow more granularity of prds control on a part bbc includes a 4-kbyte decram that can be used if compression is not used or is not available. 3 sram keep-alive power behavior the sram has three keep-alive power pins (vddsram1, vddsram2, and vddsram3). these pins provide keep-alive power to the sram arrays in the calram modules and the dptram modules. the vddsram1 pin powers the 32-kbyte calram a during keep-alive while power is off to the mpc565 (except for the keep-alive power supplies). calram a keeps all of its 32 kbytes powered during power down. the vddsram2 pin powers the 4-kbyte calram b module. the vddsram3 pin powers the dptram modules during keep-alive as well as during normal operation. the calram modules only power their arrays from the vddsram pins during keep-alive. during normal operation, they are powered by the normal internal vdd of the part. the dptram modules (6 kbytes and 4 kbytes) and the 4-kbyte decram in the bbc module power their arrays via the vddsram3 pin during keep-alive and are supplied by vdd during normal operation. 4 mpc565 memory map the internal memory map is organized as a single 4-mbyte block. this is shown in figure 3. this block can be moved to one of eight different locations. the internal memory space is divided into the following sections: flash memory (1 mbyte) ? u-bus memory static ram memory (36 kbytes calram) ? l-bus memory control registers and imb3 modules (64 kbytes), partitioned as ? usiu and flash control registers ? uimb interface and imb3 modules ? calram and readi control registers (l-bus control register space) the internal memory block can reside in one of eight possible 4-mbyte memory spaces. these eight locations are the first eight 4-mbyte memory blocks starting with address 0x0000 0000, as shown in figure 2. there is a user programmable register in the usiu to configure the internal memory map to one of the eight possible locations. programmability of internal memory map location allows multiple chip system. the imb3 address space block in figure 3 shows memory allocation for imb3 modules. it does not show the actual memory space required for individual modules. all modules are mapped to the low address, numerically, of the memory allocated for that module in the imb3 address space. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mpc565/mpc566 product brief 11 additional mpc565 differences figure 2. memory map 0x0000 0000 0xffff ffff 0x0100 0000 0x00ff ffff 0x01ff ffff 0x00c0 0000 0x00bf ffff 0x0080 0000 0x007f ffff 0x0040 0000 0x003f ffff 0x01c0 0000 0x01bf ffff 0x0140 0000 0x013f ffff 0x0180 0000 0x017f ffff internal 4-mbyte memory block (resides in one of eight locations) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
12 mpc565/mpc566 product brief motorola additional mpc565 differences figure 3. internal memory block calram/ readi control 256 bytes 0x38 00ff 0x38 0100 reserved (l-bus control) ~32 kbytes 4-kbyte overlay section 0x30 7fff 0x2f ffff 0x30 0000 0x3f 6fff 0x3f 7000 0x08 0000 0x3f 7fff 0x3f 8000 0x00 0000 usiu & flash control 16 kbytes uimb i/f & imb modules 32 kbytes 0x07 ffff 0x10 0000 calram_a (32 kbyte) reserved for flash (2,016 kbytes) 0x2f bfff 0x30 8000 0x37 ffff reserved for imb 480 kbytes reserved (l-bus mem) 444 kbytes 0x38 4000 uc3f_b flash 512 kbytes 0x38 0000 0x38 3fff 0x0f ffff uc3f_a flash 512 kbytes 0x2f c000 calram_b (4 kbyte) 0x3f ffff all 4-kbytes can be 0x2f 7fff ox2f 8000 overlay section 0x30 0000 0x30 7fff dptram_ab (6 kbytes) qsmcm_a (1 kbytes) mios14 (4 kbytes) toucan_a (1 kbytes) toucan_b (1 kbytes) uimb control registers (128 bytes) tpu3_a (1 kbytes) tpu3_b (1 kbytes) qadc64_a (1 kbytes) qadc64_b (1 kbytes) dptram_ab reserved (2 kbytes) usiu control registers uc3f_a control uc3f_b control 0x2f c000 0x2f c87f qsmcm_b (1 kbytes) 0x30 7900 0x30 7000 0x30 6000 0x30 5800 0x30 5400 0x30 4c00 0x30 4800 0x30 4400 0x30 4000 0x30 3800 0x30 2000 0x30 7400 dptram_c (4 kbytes) 0x30 1000 dptram_c 0x30 0040 reserved (1 kbytes) reserved (896 bytes) tpu3_c (1 kbytes) 0x30 5c00 0x30 7800 dlcmd2 (16 bytes) 0x2f c800 0x2f c840 0x30 7f80 toucan_c (1 kbytes) reserved (3952 bytes) 0x30 0080 0x30 0090 0x30 5000 registers (64 bytes) registers (64 bytes) decram 0x2f 8fff 0x2f 9000 4 kbytes 0x2f 9fff reserved bbc control registers 0x2f a000 8 kbytes (64 bytes) (64 bytes) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mpc565/mpc566 product brief 13 additional mpc565 differences 5 mpc565 pinout diagram figure 4 shows the pinout for the mpc565. figure 4. mpc565 pinout diagram 1234567891011121314151617181920212223242526 a vdd an64_b_ vrh vrl an84 an80 an48_a_ an53_a_ ma1_pqa1 vdda vssa an76_b_ an72_b_ ma0_pqa0 an67_b_ an65_b_ qvddl a_tpuch2 a_tpuch4 a_tpuch6 a_tpuch10 a_tpuch14 a_tpuch1 b_tpuch5 b_tpuch10 b_tpuch12 b_tpuch14 vss a b vss vdd an44_anw_ a_pqb0 altref an85 an81 an49_a_ an52_a_ ma0_pqa0 an56_a_ an58_a_ an77_b_ an73_b_ ma1_pqa1 an69_b_ an66_b_ qvddl etrig2 a_tpuch5 a_tpuch8 a_tpuch11 a_t2clk b_tpuch3 b_tpuch6 b_tpuch7 b_tpuch13 vss vdd b c vddrtc vss vdd an45_anx_ a_pqb1 an87 an83 an46_any_ a_pqb2 an50_a_ an54_a_ ma2_pqa2 an57_a_ an79_b_ an75_b_ an71_b_ an70_b_ qvddl etrig1 b_cnrx0 a_tpuch9 a_tpuch12 a_tpuch15 b_tpuch4 b_tpuch11 b_tpuch8 vss vdd b_tpuch15 c d extal32 vddsram2 vss vdd vddh an86 an82 an47_anz_ a_pqb3 an51_a_ an55_a_ an59_a_ an78_b_ an74_b_ ma2_pqa2 an68_b_ qvddl vddh a_tpuch3 a_tpuch7 a_tpuch13 a_tpuch0 b_tpuch9 nvddl vss vdd b_tpuch2 b_tpuch0 d e xtal32 b_cntx0 vddsram1 vss vdd b_tpuch1 b_t2clk mpwm17 e f vssrtc c_tpuch14 c_tpuch15 nvddl mpwm5_ mpio32b6 mpwm18 mda11 mda13 f g c_tpuch10 c_tpuch11 c_tpuch12 vddsram3 mda12 mda27 mda28 mda29 g h c_tpuch9 c_tpuch7 c_tpuch8 c_t2clk mda30 mda31 mpwm0 mpwm1 h j c_tpuch6 c_tpuch5 c_tpuch3 c_tpuch13 mpwm3 mpwm2 mpwm16 mpwm20_ mpio32b11 j k c_tpuch2 c_tpuch1 c_tpuch0 c_tpuch4 mda15 mda14 mpwm21_ mpio32b12 c_cntx0_ mpio32b13 k l mdi_0 tck_dsck mdi_1 mcki vss vss vss vss vss vss c_cnrx0_ mpio32b14 mpio32b15 mpwm19 vf0_ l m tdi_dsdi evti_b rsti_b msei_b vss vss vss vss vss vss vf1_ vf2_ mpwm4_ mpio32b5 vfls0_ mpio32b3 m n tms mdo_4_ mpio32b10 mdo_6_ mpio32b8 mdo_5_ mpio32b9 vss vss vss vss vss vss vddh vfls1_ mpio32b4 b_pcs0_ss __bqgpio0 b_pcs1_ qgpio1 n p mdo_7_ mpio32b7 jcomp mcko mdo_0 vss vss vss vss vss vss b_eck b_miso_ qgpio4 b_pcs3_ j1850_tx b_mosi_ qgpio5 p r mdo_1 tdo_dsdo mdo_2 iwp1_ vss vss vss vss vss vss b_sck_ b_pcs2_ qgpio2 b_txd1_ b_txd2_ r t mdo_3 mseo_b iwp0_ sgpioc6_ ptr_b vss vss vss vss vss vss a_txd1_ a_miso_ qgpio4 b_rxd2_ j1850_rx a_sck_ (c3f_clk) t u addr_ sgpioa16 addr_ sgpioa17 addr_ nvddl a_pcs2_ qgpio2 a_rxd1_ (c3f_sup1) a_mosi_ qgpio5 a_pcs3_ (c3f_iout) u v addr_ sgpioa18 addr_ sgpioa19 addr_ addr_ sgpioa10 a_pcs0_ qgpio0 a_txd2_ a_rxd2_ (c3f_sup2) b_rxd1_ v w addr_ sgpioa20 addr_ sgpioa21 addr_ sgpioa11 addr_ sgpioa12 nvddl vflash a_pcs1_ pullsel w y addr_ sgpioa22 addr_ sgpioa23 addr_ sgpioa13 addr_ sgpioa14 vddf extclk a_cntxo kapwr y aa addr_ sgpioa24 addr_ sgpioa25 addr_ sgpioa15 addr_ sgpioa30 poreset_b a_cnrxo vssf xtal aa ab addr_ sgpioa26 addr_ sgpioa27 addr_ sgpioa31 qvddl hreset_b irq6_b_ modck2 rstconf_ b_texp extal ab ac addr_ sgpioa28 nc qvddl vss vdd vddh data_ sgpiod29 data_ sgpiod27 nvddl data_ sgpiod24 data_ sgpiod22 data_ sgpiod20 nvddl sgpioc7_ ut_b_lwp0 nvddl we_b_at1 nvddl cs3_b bi_b_sts_b vddh vdd vss qvddl sreset_b irq7_b_ modck3 vsssyn ac ad addr_ sgpioa29 qvddl vss vdd nc data_ sgpiod31 data_ sgpiod30 data_ sgpiod28 data_ sgpiod26 data_ sgpiod25 data_ sgpiod23 data_ sgpiod21 data_ sgpiod19 irq4_b_at2 _sgpioc4 tea_b irq2_b_cr_b_s gpioc2 we_b_at2 cs1_b tsiz0 b0epee clkout vdd vss qvddl irq5_b_ modck1 xfc ad ae qvddl vss vdd data_ data_ data_ data_ data_sgpiod9 data_sgpiod1 1 data_ sgpiod13 data_ sgpiod15 data_ sgpiod17 irq3_b_kr_b _retry_b_ sgpioc3 bb_b_ rd_wr_b oe_b we_b_at0 cs0_b burst_b ts_b bdip_b nc vdd vss qvddl vddsyn ae af vss vdd data_ data_ data_ data_ data_ data_sgpiod1 0 data_sgpiod1 2 data_ sgpiod14 data_sgpiod1 6 data_ sgpiod18 irq1_b_rsv_b_ sgpioc1 bg_b_vf0 _lwp1 br_b_vf1 irq0_b_ sgpioc0 we_b_at3 cs2_b tsiz1 ta_b epee engclk_ nc vdd vss qvddl af 12345678910111213141516171819202122232425 26 _trst_b note: this is a top down view of the balls. mpio32b0 mpio32b2 mpio32b1 qgpo2 qgpo1 qgpio6 qgpio6 qgpo1 qgpio3 qpi1 ss_b_ qgpo2 qpi2 qgpi1 qgpio1 sgpioc5_ buclk _iwp2 irqo vf2_iwp3 sgpiod7 sgpiod8 sgpiod6 sgpiod5 sgpiod3 sgpiod4 sgpiod2 sgpiod1 sgpiod0 sgpioa9 sgpioa8 frz_ vfls0 vfls1 pqb0 pqb4 pqb5 pqb6 pqa4 pqa6 pqa5 pqa3 pqb7 pqa4 pqa5 pqa7 pqa7 pqa6 pqa3 pqb3 pqb5 pqb7 pqb4 pqb6 pqb2 pqb1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
14 mpc565/mpc566 product brief motorola additional mpc565 differences this page intentionally left blank f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mpc565/mpc566 product brief 15 additional mpc565 differences this page intentionally left blank f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mpc565pb/d how to reach us: usa/europe/locations not listed: motorola literature distribution p.o. box 5405, denver, colorado 80217 1-303-675-2140 or 1-800-441-2447 japan: motorola japan ltd. sps, technical information center 3-20-1, minami-azabu minato-ku tokyo 106-8573 japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd. silicon harbour centre, 2 dai king street tai po industrial estate, tai po, n.t., hong kong 852-26668334 technical information center: 1-800-521-6274 home page: http://www.motorola.com/semiconductors information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the u.s. patent and trademark office. digital dna is a trademark of motorola, inc. the described product contains a powerpc processor core. the powerpc name is a trademark of ibm corp. and used under license. all other product or service names are the property of their re spective owners. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola, inc. 2003 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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